Mentor Graphics and Atmel Announce OEM Agreement to Provide Design Flow for Programmable System-on-Chip Solutions
SAN JOSE, Calif. & WILSONVILLE, Ore.--(BUSINESS WIRE)--April 3,
2002--Mentor Graphics Corporation (Nasdaq:MENT - news) and Atmel Corporation
(Nasdaq:ATML - news) announced today an agreement to provide a comprehensive
design flow for Atmel's award winning programmable system-on-chip
(SoC) solutions, enabling embedded system designers to significantly
increase productivity and accelerate time-to-market.
Under the agreement, Atmel will license three premier tools from
Mentor Graphics, including customized versions of the Seamless®
co-verification environment, the ModelSim® HDL simulator and
LeonardoSpectrum(TM) synthesis tools.
These tools are integrated along with Atmel's FPGA place & route
tools and AVR Studio® into Atmel's System Designer(TM) programmable
SoC design environment for the design and verification of Atmel's
FPSLIC(TM) (Field Programmable System Level IC) programmable SoCs.
Atmel's AVR Studio is a complete microcontroller code development
environment that includes a compiler, debugger and instruction set
simulator (ISS). The result is a unified environment for the
co-development and co-verification of both the integrated AVR®
processor code and the HDL hardware design FPGA portions of
programmable SoCs.
The System Designer design and co-verification environment that
results from the integration of the Mentor and Atmel tools allows the
FPGA's HDL design to be verified concurrently with the debugging of
the MCU code. The designer has full visibility into the processor's
program counter, memory, registers and peripherals and into the
performance of the FPGA, at every stage during the HDL simulation.
"Mentor Graphics is the only EDA company that has addressed and
solved the issue of designing and verifying programmable SoC devices.
No other EDA vendor has as comprehensive and integrated a solution,"
said Joel Rosenberg, director of PSLI products for Atmel. "Our System
Designer tool suite provides the only comprehensive design solution
for programmable SoCs. We could not have created our design flow
without Mentor Graphics."
"Our sustained partnership with Atmel demonstrates Mentor's
commitment to providing comprehensive system-level solutions for all
FPGA-based products and specifically for programmable SoCs," said Anne
Sanquini, vice president and general manager of the HDL Design
division, Mentor Graphics. "Atmel continues to push the limits of
programmable system-level integration and Mentor's tools continue to
support its latest innovations, while at the same time minimizing
design risk and reducing design cycles."
Seamless Addresses Co-Verification Needs
Seamless allows users to validate hardware/software interfaces in
a virtual and unified environment. Co-verification provides a
high-visibility design debug environment enabling the early detection
and correction of potential software code and/or hardware logic
errors. Tailored to the FPSLIC architecture, Seamless is designed to
address the co-verification needs of Atmel's customers. The Seamless
tool uses pre-existing knowledge of the embedded processor and memory
system to eliminate the configuration stage traditionally associated
with co-verification tools, making co-verification a push-button
process in the System Designer tool suite.
ModelSim Enables Simulation and Design Debug
The Mentor Graphics ModelSim HDL simulator tool is aimed at
today's multi-million gate ASIC and FPGA designs. The need to detect
errors in the development cycle, before synthesis and place and route,
becomes increasingly important in improving engineering productivity.
ModelSim provides FPSLIC designers access to a complete VHDL or
Verilog-based design flow, including RTL and gate-level HDL simulation
and synthesis.
LeonardoSpectrum Offers Superior Synthesis Capabilities
The Mentor Graphics LeonardoSpectrum synthesis tool allows Atmel
users to create FPGA designs in VHDL or Verilog using one synthesis
environment. LeonardoSpectrum eases the creation and management of
FPSLIC designs used in markets such as industrial control,
communications, broadband, wireless and multimedia. Combining
push-button ease-of-use features and sophisticated design strategies,
LeonardoSpectrum allows Atmel designers to carefully control and
optimize FPGA designs to meet their exact design requirements.
HDL Planner
In addition to the Mentor Graphics and AVR Studio development
tools, Atmel's System Designer has an HDL Planner module that allows
firmware developers who are not familiar with hardware description
languages to rapidly create syntactically correct Verilog or VHDL
designs for the embedded FPGA logic inside FPSLIC. Using a top down
design flow, the designer creates hardware components using any of
more than 50 point-and-click macro generators. In addition, HDL
Planner will automatically generate architecturally optimized layout
and post layout Verilog or VHDL models for the FPGA portion of the
design.
Pricing and Availability
Available today, Atmel's ATSTK94 FPSLIC Starter Kit contains a
four-month software license and an FPSLIC prototyping hardware kit for
$495. System Designer version 2.0 is available now for $995 for an
annual subscription, or $2,495 for a perpetual license.
About Atmel
Founded in 1984, Atmel Corporation is headquartered in San Jose,
Calif., with manufacturing facilities in North America and Europe.
Atmel designs, manufactures and markets worldwide, advanced logic,
mixed-signal, nonvolatile memory and RF semiconductors. Atmel is also
a leading provider of system-level integration semiconductor solutions
using CMOS, BiCMOS, SiGe, and high-voltage BCDMOS process
technologies.
About Mentor Graphics Corporation
Mentor Graphics Corporation is a world leader in electronic
hardware and software design solutions, providing products, consulting
services and award-winning support for the world's most successful
electronics and semiconductor companies. Established in 1981, the
company reported revenues over the last 12 months of more than $600
million and employs approximately 3,100 people worldwide. Corporate
headquarters are located at 8005 S.W. Boeckman Road, Wilsonville,
Oregon 97070-7777; Silicon Valley headquarters are located at 1001
Ridder Park Drive, San Jose, California 95131-2314. World Wide Web
site: www.mentor.com.
Mentor Graphics, ModelSim and Seamless are registered trademarks,
and LeonardoSpectrum is a trademark of Mentor Graphics Corporation.
Atmel, AVR and AVR Studio are registered trademarks, and System
Designer and FPSLIC trademarks of Atmel Corporation. All other company
or product names are the registered trademarks or trademarks of their
respective owners.
Contact:
Atmel Corporation
Joel Rosenberg, 408/436-4290
jrosenberg@atmel.com
or
Mentor Graphics Media Relations
Mark Mohammadpour, 503/552-3734
mmohammadpour@webershandwick.com
